发明名称 BUILT-IN MICROPROCESSOR TYPE MEMORY CONTROLLING STRUCTURE
摘要 <p>PURPOSE: To execute flexible byte collection at a microprocessor level by providing the memory control structure with a programmable byte collecting function. CONSTITUTION: A CPU 102 has 32-bit word size, 16-bit half word size and 8-bit byte size. An external memory bus 114 has various control signals for controlling a transaction or the like on the bus and can be accessed from the outside of, a chip 100. A bus interface unit(BTU) 104 has a logic circuit 116 for byte collection, and when a bus reading transaction is started, an input signal is validated and byte collection is executed. A flexible option can be set up in a DRAM control circuit 120 so as to use a DRAM having various access speeds and an automatic waiting condition generator (AWC) 118 independently controls processor instructions in a PROM 108 and the address space of I/O data. The AWC 118 can be invalidated.</p>
申请公布号 JPH05120124(A) 申请公布日期 1993.05.18
申请号 JP19910290711 申请日期 1991.10.09
申请人 LSI LOGIC CORP 发明人 MAIKERU FUTSUSHIO;ROBAATO ERU KOOKU
分类号 G06F12/04;G06F12/00;G06F12/08;G06F13/40;G06F15/78;G11C7/10 主分类号 G06F12/04
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