发明名称 |
FLOATING POINT ARITHMETIC TWO CYCLE DATA FLOW |
摘要 |
A processor for performing floating point arithmetic operations is provided that includes a circuit that performs a first floating point arithmetic operation on a set of operands in a first cycle and and a second floating point arithmetic operation on an operand and a result of the first floating point arithmetic operation during a second cycle. A control circuit is provided for, in a third cycle, transferring a result of the second floating operation to the first floating point circuit for a first floating point operation in a next successive cycle while rounding the result of the second floating point operation.
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申请公布号 |
US5212662(A) |
申请公布日期 |
1993.05.18 |
申请号 |
US19900580892 |
申请日期 |
1990.09.11 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
COCANOUGHER, DANIEL;MONTOYE, ROBERT K.;NGUYENPHU, MYHONG;RUNYON, STEPHEN L. |
分类号 |
G06F7/544;G06F7/57 |
主分类号 |
G06F7/544 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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