| 摘要 |
PURPOSE:To extract a synchronization clock and serial binary data in an input signal subject to Manchester coding without use of a PLL circuit. CONSTITUTION:The circuit consists of a delay section 2 delaying an input signal subject to Manchester coding, a 1st exclusive OR section 3 exclusive ORing between the input signal and an output of the delay section 2, a 1st flip-flop 6 receiving the input signal at its data input terminal and an output of the exclusive OR section 3 at its timing terminal, a 2nd exclusive OR section 7 taking exclusive OR between an output of the flip-flop 6 and an output of the delay section 2, a 2nd flip-flop 8 receiving an output of the flip-flop 6 at its data input terminal and an output of an exclusive OR section 7 at its timing terminal, and a means extracting an output of the exclusive OR section 7 as a periodic clock in the input signal and extracting an output of the flip-flop 8 as serial binary data in the input signal. |
