| 摘要 |
PURPOSE:To obtain the input buffer circuit which can inhibit the transmission of noise pulses, by inserting a capacitor between the threshold voltage terminal and the input terminal. CONSTITUTION:The input buffer circuit consists of the differential transistors(TR)Q1,Q2, and the reference voltage Vref being the logic threshold voltage is fed to the base of TRQ1 and the input pulse signal Vin is to the base of TRQ2. The capacitor C connects the base between TRQ1 and Q2 to obtain the output signal Vout phase with Vin at the collector of TRQ1. If noise signal A is mixed to the input signal Vin and if the time width of the noise signal A is smaller than the charging time constant of the capacitor C, no noise signal is mixed in the output signal Vout. Since normal input pulse signal Vin has longer pulse width than said time constant, the output signal Vout is obtained with a delay of this time constant. |
