| 摘要 |
<p>The present invention relates to a dynamic RAM controller and to a circuit for driving a plurality of dynamic RAM banks. By making a dynamic RAM controller provides its current mode of operation (access/refresh) at its output. It is possible to extend at will the possibilities of addressing of the controller itself; as a result, a sole controller is capable of handling several memory banks by merely adding a decoding logic for selection of the bank during the access operation mode. In this manner it is further obtained the advantage of having the refresh time tied only to the dimension of the memory bank and not to the number of memory banks since the refresh occurs in parallel on all memory banks. <IMAGE></p> |
