发明名称 |
High speed testing of field-effect transistors. |
摘要 |
A testing circuit for testing field-effect transistors of, for example, a random access memory includes weak N-channel pull-down field-effect transistors and weak P-channel pull-up field-effect transistors for testing field-effect transistors of opposite type to be tested. The weak field-effect transistors are placed in series with the opposite type of field-effect transistors. When the series coupled field-effect transistors are turned on, the voltage at the common node of the field-effect transistors is sensed to determine whether the common node is pulled-up or pulled-down in potential to indicate whether a field-effect transistor under test is functional. <IMAGE> |
申请公布号 |
EP0541240(A1) |
申请公布日期 |
1993.05.12 |
申请号 |
EP19920309058 |
申请日期 |
1992.10.05 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
BOWLES, JAMES E. |
分类号 |
G01R31/26;G01R31/27;G11C29/50;H01L21/66;H01L21/822;H01L21/8244;H01L27/04;H01L27/11 |
主分类号 |
G01R31/26 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|