| 摘要 |
A digital mixer circuit is disclosed in which a plurality of digital signals are shifted in bit and applied to a plurality of selectors (11-18), which are operated in accordance with a predetermined weighting coefficient, thereby producing a plurality of selected data trains shorter in bit length than the input signals. The plurality of selected data trains are added to each other to calculate the sum. Since the input signals are added with the bit length thereof shortened, the rate of increase in the number of adder gates is smaller with the increase in the number of steps in which the mixing ratio is changeable, thereby facilitating the circuit integration. <IMAGE> |
