| 摘要 |
<p>A low power complementary MOSFET buffer circuit includes an input complementary MOSFET inverter (102) with a plurality of serially coupled diode-connected complementary MOSFETs (116,118) and an output complementary MOSFET inverter (104). An input digital signal drives one of the input inverter's MOSFET gates, and passes through the diode-connected MOSFETs to be biased, or level-shifted, prior to driving the input inverter's other MOSFET gate. Using the input digital signal directly and its biased equivalent ensures that, when each of the input inverter's MOSFETs is turned "off " in accordance with the logic level of the input digital signal, it is turned off more fully, thereby minimizing power dissipation. The inverted digital signal outputted from the input inverter drives both of the output inverter's MOSFET gates. The original input digital signal also drives one of the output inverter's MOSFET sources, whereby the low-to-high transition time of the output digital signal is reduced. <IMAGE></p> |
