| 摘要 |
66446-462 An address detection circuit for high-speed detection of long addresses by the use of a memory addressable at a shorter address length than the length of the address to be detected. The novel circuit comprises a subfield address generator which generates N (greater than 1) subfield addresses obtained by dividing an input address by N. A subfield indicating signal generator generates a subfield indicating signal for indicating the order in which these N subfields are inputted. The subfield and subfield indicating signal forms a memory address, which is generated N times. An address comparator compares the memory addresses and memory addresses stored therein and generates comparison signals. A decision circuit decides that, when the comparison signals prove to be identity signals N times, the input address represents the address to be detected and generates an address detection signal. |
