| 摘要 |
A data processor having an instruction varied set associative cache boundary access capability provides reduced power consumption and maintains data processor performance. Queued data processor operation codes are partially decoded within an intermediate stage of an instruction pipe of the data processor to provide information on pending instructions. The information provided determines if a pending instruction will require either a full or a partial output line of information from the set associative cache. When the provided information from the instruction pipe indicates that an instruction will require a full output line of information to complete execution, the set associative cache provides the full output line of information. Otherwise, the set associative cache provides only a partial output line of information.
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