发明名称 FRAME SYNCHRONIZING CIRCUIT FOR DIGITAL TRANSMISSION SYSTEM
摘要 <p>PURPOSE:To prevent a frame synchronization step-out and to smoothly perform pull-in by changing the detection range of the frame synchronizing bit at the forward protection time and the backward protection time. CONSTITUTION:The circuit is provided with a detection circuit part 10 inputting data rows 11, 12, 13,...1n and detecting the frame synchronizing bit set for each frame synchronizing establishment according to the control signal from a protection circuit 30 and outputting detection results 21, 22, 23,...2n to a discrimination circuit 20, the discrimination circuit 20 discriminating the detection result each time the timing pulse to be outputted from a frame synchronizing counter 40 is inputted and outputting the discrimination result, and a protection circuit 30 protecting the synchronization based on the discrimination result and outputting a control signal according to the frame synchronizing establishment state.</p>
申请公布号 JPH05114898(A) 申请公布日期 1993.05.07
申请号 JP19910302438 申请日期 1991.10.22
申请人 NEC CORP 发明人 MUTO HIDEYUKI
分类号 H04J3/06;H04L7/08 主分类号 H04J3/06
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