Triple redundancy computer system for data transfer - has three independently clocked computers linked to controller and common data bus, and logic circuit to compare block signals with threshold values to isolate faulty computer

摘要

The computer system comprises three computers (10,20,30) operating in parallel, linked by a common data bus (40) and controller (60). Each computer has an independent clock source (CLK1,CLK2,CLK3). The clock signals are compared to threshold levels relating to time, and any computer which does not fall into the tolerance band is isolated. The tolerance values may either be stored by the controller or generated w.r.t. a time slot. The controller contains a timer, logic circuitry and input register. ADVANTAGE - Increase data transfer safety, simplified design using single data bus.