| 摘要 |
Prior art: Alternating transmission of addresses and data on the same bus lines. Technical problem: Transmission of variable-length data blocks. Basic concept: One of the remaining signals present in any case (chip select, CS, read, write) indicates the block length. The first time slot after this signal has been set is intended for an address (start address), all subsequent time slots up until the signal is reset are intended for data. Solution: A counter (FF1, FF2, FF3) counts down the first time slots of a data block and sequentially enables receivers (ZH, ZL) or transmitters for the first (AH) and any further (AL) address bytes, transmitters or receivers (MEM) for data (D1, D2, D3) and lastly a counting clock pulse (ZS) for incrementing the address. The counter is reset at end of block. Advantage: At the beginning of the transmission of a data block, its length does not yet need to be known. <IMAGE> |
