| 摘要 |
<p>A monolithic phaselock loop circuit (PLL) for controlling the phase and frequency of a free-running oscillator to compensate for process induced variations in the VCO natural frequency and to extend the fpull-in range by +/-50% of the frequency of the reference clock. The PLL is comprised of a VCO, a digital phase comparator, a digital frequency divider and a digital sequential phase error detector (SPED). The SPED circuit comprises two up-down counters, one to control the phase; the other, the frequency; a first one-shot circuit to detect every level transition of the reference clock and a second one-shot circuit to provide a pulse for every falling edge of the reference clock; and a shift register to store the value of the phase comparator thereby providing indication of a frequency lock between the free running external oscillator and the VCO. <IMAGE></p> |
