| 发明名称 |
Planar FET-SEED integrated circuits. |
| 摘要 |
<p>Structure and method for fabricating FETs and quantum well diodes on the same semi-insulating substrate where the FET is provided with enhanced protection from spurious voltages. The structure uses a deeply buried p-layer (17) in a semi-insulating substrate (14) partitioned to isolate the FET portion (40) of the substrate. The same buried p-layer can be partitioned to provide the p-regions of quantum well diodes (30). <IMAGE></p> |
| 申请公布号 |
EP0540233(A1) |
申请公布日期 |
1993.05.05 |
| 申请号 |
EP19920309610 |
申请日期 |
1992.10.21 |
| 申请人 |
AMERICAN TELEPHONE AND TELEGRAPH COMPANY |
发明人 |
CHIROVSKY, LEO MARIA FREISHYN;D'ASARO, LUCIAN ARTHUR;PEI, SHIN-SHEM;WOODWARD, TED KIRK |
| 分类号 |
H01L21/822;G02F3/02;H01L27/04;H01L27/095;H01L27/144;H01L27/15;H01L29/80;H01L29/86;H01L31/10 |
主分类号 |
H01L21/822 |
| 代理机构 |
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代理人 |
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| 地址 |
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