| 摘要 |
<p>A track traverse detecting circuit (4) for generating a count-out signal with precision in addressing high-speed traverse operations appropriately. The circuit includes a tracking zero cross (TZC) signal generating circuit (33), two delay circuits (37,38), an edge detecting circuit (34) and a mirror signal generating circuit (32). The TZC signal generating circuit (33) generates a TZC signal at the zero cross timing of a tracking error signal. The TZC signal is then delayed by one of the two delay circuits (37,38) by an appropriate time in accordance with the traverse speed for access to a desired track. Edges of the delayed TZC signal are detected by the edge detecting circuit (34). A mirror signal output by the mirror signal generating circuit (32) is sampled at the timing of the detected TZC signal edges. The output of the sampling is provided accurately as the count-out signal. <IMAGE></p> |
