| 摘要 |
A processor includes a mechanism in which logical addresses are translated into physical addresses by a translation lookaside buffer (TLB) 11 within one clock cycle. This is achieved by the TLB translation being performed in parallel with the calculation of the effective address, the effective address being calculated by a "base-plus-displacement/offset" computation. Such a computation usually does not cross a page boundary, that is, the upper 20 bits, which correspond to the logical page number, are the same after the add. Therefore, only the upper 20 bits of the logical address are translated by the TLB, since it is assumed that these will not change. After the add, if the upper 20 bits did not change, then the 20 physical address bits from the TLB plus the lower 12 bits from the address computation are concatenated to produce the complete correct 32-bit physical address within a single clock cycle. If, however, the upper 20 bits did not change then a signal is generated which enables the translation using the correct logical address, as computed by the effective address generation hardware, to be performed. <IMAGE> |
