摘要 |
<p>A digital data system (10) includes a circuit (18) for controlling data transfer between a byte wide device, such as a SCSI disk drive (12), to a four byte wide pathway such as VME bus (16). The control circuit (18) effects selective control of data transfer of an odd byte, an even byte, a short word (two parallel bytes), or a long word (four parallel bytes). The control circuit includes a FIFO memory (20), prefetch registers (22), (24), (26), (28), MUXs (30), (32), (34), (36), a VME data register (38), a state machine (40) and DMA controller (42). <IMAGE></p> |