Packet switching system capable of reducing a delay time for each packet.

摘要

In a packet switching system having input ports (20-1-1 to 20-8-8) supplied with input packets and output ports (21-1-1 to 21-8-8) producing output packets, each of time stampers (22-1-1 to 22-8-8) connected to the input ports assigns a time stamp to the input packet supplied thereto to produce a time stamped packet. Connected to the time stampers, each of primary switches (23-1 to 23-8) carries out a primary switching operation on the time stamped packets supplied thereto so as to connect input lines thereof and output lines thereof in one-to-one correspondence to produce primary switched packets. Connected to the primary switches in a cross link connection fashion, each of secondary switches (24-1 to 24-8) carries out a secondary switching operation on the primary switched packets on the basis of destination addresses thereof in sequence to produce secondary switched packets. Connected to the secondary switches in the cross link connection fashion, each of ternary switches (25-1 to 25-8) corrects sequence of the secondary switched packets on the basis of the time stamps assigned thereto to produce sequence corrected packets and then carries out a ternary switching operation on the sequence corrected packets on the basis of the destination addresses thereof to produce ternary switched packets. Each output port produces each ternary switched packet as each output port.