| 摘要 |
<p>An arithmetic logic unit includes first and second buses for efficient operations upon multiple-bit operands. The arithmetic logic unit includes, in addition to the first and second buses, a shift register having an input coupled to the first bus and an output, a summer having a first input coupled to the shift register output, a second input coupled to the second bus, and an output, and an accumulator having an input coupled to the summer output and an output coupled to the first bus. The arithmetic logic unit further includes a buffer having an input also coupled to the summer output and an output coupled to the second bus. The summer provides two's compliment inversion when required and the shift register performs sign bit force zero, right shifting, and masking operations. In addition, an overflow detector and overflow correction detect and correct overflow conditions without requiring additional operating cycles.</p> |
