发明名称 |
DRAM Cell with trench capacitor and vertical channel in substrate |
摘要 |
A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with the capacitor formed in a trench in a substrate and the transistor channel formed by epitaxial growth on the substrate. The transistor source and drain are insulated from the substrate, and the transistor may be adjacent the trench or on the upper portion of the trench sidewalls. Signal charge is stored on the capacitor plate insulated from the substrate.
|
申请公布号 |
US5208657(A) |
申请公布日期 |
1993.05.04 |
申请号 |
US19910733916 |
申请日期 |
1991.07.22 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
CHATTERJEE, PALLAB K.;MALHI, SATWINDER;RICHARDSON, WILLIAM F. |
分类号 |
H01L21/334;H01L21/8242;H01L27/108 |
主分类号 |
H01L21/334 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|