发明名称 Unsigned integer multiply/divide circuit
摘要 An unsigned integer multiply/divide circuit is implemented with an unconventional non-restoring division algorithm which always subtracts the divisor from the partial dividend regardless of whether the divisor is greater than the partial dividend or not, a hybrid carry lookahead and carry select adder construction where both portions run in parallel, and control lookahead features which avoid interim calculation wait delays. The division algorithm is further modified in order that the same hardware configuration primarily consisting of storage registers, an adder, a multiplexer, and a shifter can be used for both multiplication and division operations.
申请公布号 US5208769(A) 申请公布日期 1993.05.04
申请号 US19910762593 申请日期 1991.09.19
申请人 ZILOG, INC. 发明人 MANDAVA, BABU S.
分类号 G06F7/50;G06F7/52 主分类号 G06F7/50
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