发明名称 SYNCHRONIZING TYPE DIGITAL CIRCUIT
摘要 PURPOSE:To facilitate the design and to secure the reliability of an LSI by devising the synchronizing type digital circuit such that the timing is made adjustable. CONSTITUTION:Plural delay elements 2 connected in series and plural fuse elements 3 connected in parallel with the delay elements 2 are interposed between an input terminal 10 of a circuit 1 operated based on a signal inputted in a required timing and a clock signal terminal 4, and the fuse elements 3 are selectively blown out after the manufacture of the LSI to change a delay of a timing signal inputted from the terminal 4 thereby adjusting the operating timing of the entire circuit.
申请公布号 JPH05110397(A) 申请公布日期 1993.04.30
申请号 JP19910299869 申请日期 1991.10.19
申请人 NEC CORP 发明人 NAKANO MASAFUMI
分类号 H03K5/13;H03K5/133 主分类号 H03K5/13
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