| 摘要 |
PURPOSE:To prevent the generation of a jitter even in the case a receiving signal in which data is not superposed extending over a long time is received by setting a frequency divider to a transmission clock and a data clock so as to satisfy a specific expression. CONSTITUTION:A phase locked circuit is provided with a first frequency divider 41a in which a transmission clock signal synchronized with a data clock signal extracted from a receiving signal is inputted and subjected to 1/M frequency division, a second frequency divider 42 for allowing an input signal to be subjected to I/N frequency division, a phase comparator 43 for outputting a signal corresponding to a phase difference of inputted outputs of a first and a second frequency dividers 41a, 42, and a voltage control crystal oscillator 45 for receiving an output of the phase comparator 43 through a loop filter 44. Also, this circuit is constituted so that an output of the voltage controlled- crystal oscillator 45 is fed back to an input of a second frequency dividing circuit 42. Moreover, a first and a second frequency dividers 41a, 42 are set to a transmission clock f1 and a data clock f2 so as to satisfy the expression. In such a way, no jitter is generated. |
