| 摘要 |
<p>PURPOSE:To provide a flip-flop circuit in which a propagation delay time till a signal at a data output terminal is in pull-up operation is small. CONSTITUTION:The control electrode of a 1st transistor(TR) 131 applying pull-up drive to a signal at a data output terminal Q connects to a 1st transfer gate 123 transferring the noninverting voltage level of input data, and a control electrode of a 2nd transistor(TR) 133 applying pull-down drive to a signal at the data output terminal Q connects to a 2nd transfer gate 125 transferring the inverting voltage level of the input data, and plural inverting means 111,113 are provided between an output node between the 1st and 2nd TRs and the control electrode of the 1st TR 131 and an odd number stage of inverting means 115 are provided between the output node and the control electrode of the 2nd TR 133.</p> |
