发明名称 DETECTION/RELEASE CIRCUIT FOR CONSECUTIVE DATA '1 OR 0'
摘要 PURPOSE:To provide a circuit where consecutive data of '1 or 0' within a prescribed period can be detected/released. CONSTITUTION:This circuit consists of a counter part 1 generating the address values of O-n, an address difference detection part 2 detecting an address from the counter part 1, an alarm detection part 3 outputting an alarm detection signal when a difference value from the address difference detection part 2 is larger than an alarm detection set point, an alarm release part 4 transmitting an alarm release signal when the difference value from the address difference detection part 2 is smaller than an alarm release set point, and an alarm output part 5 releasing an alarm by the alarm release signal from the alarm release part 4 are provide.
申请公布号 JPH05108416(A) 申请公布日期 1993.04.30
申请号 JP19910266635 申请日期 1991.10.16
申请人 FUJITSU LTD 发明人 NOGUCHI TOSHIHIRO
分类号 G06F11/32 主分类号 G06F11/32
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