发明名称 Memory circuit with feedback shift register and comparator - has defined addresses for test data supplied by built-in test circuit for functional check on memory
摘要 The memory (1), having data and address input (2, 4) from separate switches (3, 5), delivers outputs from a predetermined sequence of addresses to the shift register (18), whose content is compared (19) with a desired value in a complete readout cycle. The test circuit (9) consists of a microprocessor (13) and a test memory (14) coupled (8) to the data input switch (3). It selects (15) either write or read mode for the memory (1), operates (11) the address input switch (5), and sets (20) the shift register (18) initially. ADVANTAGE - A check on correct operation of the memory is easily applied without recourse to very complex circuitry.
申请公布号 DE4135084(A1) 申请公布日期 1993.04.29
申请号 DE19914135084 申请日期 1991.10.24
申请人 PHILIPS PATENTVERWALTUNG GMBH, 2000 HAMBURG, DE 发明人 BEHRENS, MICHAEL, DR.-ING.;RENNINGER, SIEGFRIED, DIPL.-ING. (FH), 8500 NUERNBERG, DE
分类号 G11C29/40 主分类号 G11C29/40
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