| 摘要 |
The apparatus prevents unnecessary operations of other devices by converting the parity of the only device in Tx/Rx operation. It includes a dip switch (Dip SW:2) for allocating the address of each processor to the I/O port of a microprocessor (CPU), an asynchronous serial Tx/Rx device (3) connected to the I/O port, and a global bus (4) connected to the asynchronous serial Tx/Rx device (3).
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