摘要 |
<p>A semiconductor device (e.g. FPGA, PROM) with an anti-fuse comprising: a semiconductor substrate (41, 61); an insulating layer (42, 62) formed on the semiconductor substrate; a lower wiring layer (43a, 63) formed above the insulating layer; an amorphous semiconductor layer (45, 65) formed above the lower wiring layer; an interlaminar insulating layer (50, 66) which is formed on the insulating layer and the amorphous semiconductor layer and has contact holes (52a, 52b) reaching the amorphous semiconductor layer; and an upper wiring layer (53, 72a) which is formed on the interlaminar insulating layer and is connected to the amorphous semiconductor layer through the contact hole (52a, 52b). When the lower wiring layer and the upper wiring layer are aluminium, preferably, a lower barrier layer (44, 64) and an upper barrier layer (46, 56a, 71a, 76a) are formed between the amorphous semiconductor layer and the lower and upper wiring layers, respectively. <IMAGE></p> |