| 摘要 |
PURPOSE:To provide the fault diagnostic circuit which diagnoses the operation of a RAM or a register file in an LSI, which has the RAM or the register file and is built in a device, without reducing the clock frequency for normal operation. CONSTITUTION:A pattern generation mode register 20 which is controlled by the control instruction outputted from a diagnostic processor 2 in the device to be diagnosed and holds and outputs a designated pattern and a test frequency register 21 which holds and outputs the frequency in test corresponding to the instruction from the diagnostic processor 2 are provided in LSIs 30 to 32 with RAMs. A pattern generating circuit 12 which outputs the address value in a RAM 16, the value to be stored in the address designated by this address value, and an expected value to be read out from the RAM 16 in accordance with outputs of these registers and an expected value collating circuit 18 which compares the value read out from the RAM 16 and the expected value with each other are provided in LSIs 30 to 32, and the RAM is diagnosed by the output result of this expected value collating circuit 18. |
