| 摘要 |
PURPOSE:To prevent a frequency fluctuation in a reference clock even when an input clock is switched in an optional timing in a clock generating circuit in which one of two asynchronous clocks is inputted selectively to a VCXO to obtain a reference clock. CONSTITUTION:A changeover controller 1 monitors phases of two frequency division clocks C, D and of a selection signal F to detect a timing when no hazard takes place, and either of them such as a 1/N frequency division clock C is selected and led to a VCXO 18. The VCXO 18 generates a clock frequency and phase frequency division clock C and the result is outputted to a reference clock generating section 19. The reference clock generating section 19 generates a reference clock and gives it to a 1/M frequency division section 14 not selected from a phase controller 2. The 1/M frequency division section 14 applies phase control to the frequency division clock D to form a frequency division clock E phase-locked with the 1/N frequency division clock C. Either of the frequency division clock E and the 1/N frequency division clock C is led to the VCXO 18. |
