发明名称 TEG MASK PATTERN FOR SEMICONDUCTOR-ELEMENT EVALUATION AND ITS LAYOUT METHOD
摘要 PURPOSE:To simultaneously observe the cross-sectional shape of a multilayer interconnection by a method wherein a plurality of sheets of a plurality of interconnection pattern groups composed of L-shaped interconnection pattern elements are overlapped sequentially by turning them by 180 deg. in the up-and-down direction perpendicular to the X-Y plane of a pattern part. CONSTITUTION:Each disconnection checking pattern 30 is constituted of the following: a pattern part 50 which is composed of a first interconnection pattern group A in which 1000 mutually similar L-shaped interconnection pattern elements P1 to P1000 have been partitioned by a halfway extraction pad 40, of a second interconnection pattern group B partitioned by a halfway extraction pad 41 and of a third residual interconnection pattern group C; and pads 42, 43 for electrical measurement use on both ends of the pattern part. When two disconnection checking patterns 30 are overlapped sequentially by turning them by 180 deg. in the up-and-down direction, it is possible to obtain a test sample which corresponds to the actual interconnection structure of two-layer interconnections. When the test sample which has been formed is cut off only in one direction, it is possible to observe the flatness of an interlayer insulating film between the individual interconnections and to observe the cross-sectional shape of the interconnections.
申请公布号 JPH05102002(A) 申请公布日期 1993.04.23
申请号 JP19910262264 申请日期 1991.10.09
申请人 SHARP CORP 发明人 UEDA HIROICHI
分类号 H01L21/66;H01L21/027 主分类号 H01L21/66
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