SEMICONDUCTOR MEMORY DEVICE

摘要

PURPOSE: To perform high-speed access to a memory cell and high integration in a semiconductor memory provided with the word line selection logic circuit of a block selection type. CONSTITUTION: The word line selection logic circuit 12 provided for each memory block is divided into the total of 32 blocks 141 -1432 . The activation/ inactivation control of the inverter of the respective blocks is performed by a switching circuit (inverter) constituted of a PMOS transistor T1 and an NMOS transistor Tc operated in response to output signals/BSWL1 from a memory block selection decoder.