| 摘要 |
PURPOSE:To simplify the bus control logic of an internal bus or the like by installing a level holding means in which one pair of CMOS inverters are crossed and coupled and which holds a logic level immediately before a corresponding bit of the internal bus. CONSTITUTION:Unit latch circuits ULT1 to ULTn which constitute a latch circuit LT function as a data holding means and hold a logic level immediately before corresponding bits of an internal bus BUS. As a result, even when outputs of n-output buffers coupled to the individual bits of the internal bus BUS are set simultaneously to a high impedance state, levels of the individual bits of the internal bus BUS are set to high levels or low levels which are fully swung according to the logic level immediately before them. Thereby, it is not required to always and alternately activate n-output buffers which are coupled to the individual bits of the internal bus BUS, and the bus control logic of the internal bus can be simplified. |
