发明名称 TIMER CIRCUIT
摘要 <p>PURPOSE:To decrease the load of a CPU when the reloading value of a timer is changed and to perform the high integration of circuit. CONSTITUTION:The timer circuit is equipped with a timer 1 to which the data of reloading registers 90, 91...9n-1 are given and which counts them, a counter 2 to which an overflowing signal OF of the timer 1 is given, a decoder 3 to decode the counted data of the counter 2, an adder 4 to add the constant to the counter 2, a ROM file 8 to store the data given to the reloading registers 90, 91...9n-1 and a base pointer 7 to store the data obtained by adding at the adder 4 and designate the address of the ROM file 8.</p>
申请公布号 JPH05100769(A) 申请公布日期 1993.04.23
申请号 JP19910261676 申请日期 1991.10.09
申请人 MITSUBISHI ELECTRIC CORP 发明人 YAMANOI GORO;KIJI AKIO
分类号 G06F1/14;H03K17/28 主分类号 G06F1/14
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