发明名称 BIT SYNCHRONIZING DEVICE
摘要 <p>PURPOSE:To obtain the bit synchronizing device of a simple constitution, which can extract a synchronization timing from a bit synchronizing signal of several bits. CONSTITUTION:An edge detecting routine 2 counts the number of sampling pulses to each code variation point of a bit synchronizing signal contained in a receiving signal S1. A jitter measuring routine 3 derives a jitter of every bit by calculating a difference between the number of sampling pulses to each code variation point which is counted, and the number of sampling pulses to each code variation point to be counted in the case there is no jitter. The jitter measuring routine 3 calculates an average value of a jitter of a 5-bit portion. A synchronization setting routine 4 corrects a jitter component with the average value of this jitter, and sets a phase so that a timing of a sampling pulse supplied to a data store part 5 becomes the center of each bit of receiving data contained in the signal S1. The data store part 5 inputs the receiving data at the timing of the sampling pulse to which the phase is set in such a way, and stores it.</p>
申请公布号 JPH05102953(A) 申请公布日期 1993.04.23
申请号 JP19910256430 申请日期 1991.10.03
申请人 SHARP CORP 发明人 SEKI YOSHINORI;KOIKE KIYOYUKI
分类号 H04L7/027;H04L25/02 主分类号 H04L7/027
代理机构 代理人
主权项
地址