TESTABLE RAM ARCHITECTURE IN A MICROPROCESSOR HAVING EMBEDDED CACHE MEMORY

摘要

A microprocessor (100) with embedded cache memory (204) is disclosed. In a "test mode" of operation, caches (204) are accessed directly from the memory interface signals. Direct writing and reading to/from the instruction and data caches (204) allows the testing of the functionality of the cache memory arrays (204). External memory interface is granted to an external master via a bus arbitration mechanism so that the test mode operation can be utilized.