| 摘要 |
PURPOSE: To provide a semiconductor memory device which is suitable when using for a cache tag memory by providing the semiconductor memory device with a parity checking circuit. CONSTITUTION: The device 10 is a dual port cache tag memory. The device has one bit known as a snoop effective bit for the respective entries in a memory. Nine pieces bits in tag data 14 are stored in respective entries in a array. The respective entries in an array 12 further have an effective bit 16, parity bit 18 and effective bit 20. The effective bit 16 is used to reset the entire part of the array 16. If the entry has a value 0 in the effective bit 16, this entry is invalid. The clear action of the entire apart of the array 12 is attained by simultaneously resetting all of the effective bits 16 for all the entries in the array. The erroneous detection of a parity error after the memory is cleared is prevented. |
