| 摘要 |
a decoder (1) for decoding the signal of Z80 CPU and the input/output address; a first and second OR gate (3,4) and a first D flip-flop (7), which are connected to the decoder (1); a second D flip-flop (9), which is connected to the decoder (1), receiving the data and the reversed clock; a third OR gate (5), which is connected to the output terminals of the first OR gate and the first D flip-flop; a fourth OR gate (6), which is connected to the reversed output terminal of the first D flip- flop and the second OR gate; a octal 3-phase buffer (11) and a quad 3-phase buffer (10), which are connected to the decoder; a modem chip circuit (2). |
