发明名称 WIRING PROCESSING SYSTEM
摘要 <p>PURPOSE:To obtain a wiring result of the small skew of a clock network by wiring to a terminal on the side of load in a position which is the fartest from a terminal on the side of a source within the clock network based on connection information of the clock network and a terminal position within the clock network on a wiring area. CONSTITUTION:First of all, a clock network detecting means 103 detects the clock network logical connection information 108. Next a main wiring means 104 wires to one of the terminals 206 on the side of the load in the position which is phisically the farthest on a branch line area means 110 from the terminal NO1 on the side of the source of a clock driver 201 within the clock network based on the each terminal position within the clock network obtained from the branch line area means 110. Thus, a main route 211 is obtained and written into the branch line area means 110. Similarly, a relay point detecting means 105 and a branch wiring means 106 repeat branch-line wiring to the remaining terminal on the side of the load as well.</p>
申请公布号 JPH0594496(A) 申请公布日期 1993.04.16
申请号 JP19910253906 申请日期 1991.10.01
申请人 NEC CORP 发明人 TAWADA SHIGEYOSHI
分类号 H01L21/82;G06F1/10;G06F17/50 主分类号 H01L21/82
代理机构 代理人
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