| 摘要 |
PURPOSE:To provide the PLL circuit with high stability and fast synchronization locking even when a voltage controlled oscillator(VCO) with a wide variable frequency width is employed. CONSTITUTION:A reference clock with an equal frequency to that of input data and an output of a VCO 1 are inputted to a 1st phase comparator 2, a voltage caused by a phase difference is inputted to an adder 4 via a low pass filter 3, its output is inputted to the VCO 1, the input data and the output of the VCO 1 are inputted to a phase comparator 5, the voltage caused by the phase difference is inputted to the adder 4 via the low pass filter 6 and added to an output voltage of the low pass filter 3 and the result of the addition is inputted to the VCO 1. |
