发明名称 CLOCK SWITCHING SYSTEM
摘要 <p>PURPOSE:To reduce the power consumption and to secure compatibility by switching the operation clock of a CPU in the state wherein the operation of the CPU is guaranteed. CONSTITUTION:The operation clock CLK is switched while the CPU 11 is reset and after the operation is switched, the CPU 11 is released from being reset. Consequently, the operation of the CPU 11 is not affected by the discontinuity of the phase of the clock at the time of the clock switching. For the purpose, the operation clock CLK is switched from a high-speed clock CLK1 to a low-speed clock CLK2 to reduce the current consumption of the CPU 11 while the operation of the CPU 11 is guaranteed. Further, the operation clock CLK of the CPU 11 can be switched matching the operation speed of application software or a hardware option to be used.</p>
申请公布号 JPH0594226(A) 申请公布日期 1993.04.16
申请号 JP19910278634 申请日期 1991.09.30
申请人 TOSHIBA CORP 发明人 NAKAMURA NOBUTAKA
分类号 G06F1/04 主分类号 G06F1/04
代理机构 代理人
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