| 摘要 |
<p>Decimation circuitry is provided having a forward shifting data section (14) receiving data samples in order including a plurality of forward decimation registers (17-20) coupled in-line and providing a forward register output. Each forward decimation register operates as a FIFO register having a decimation depth. A backward shifting data section (16) includes a plurality of backward decimation registers (21-23) having a decimation depth coupled in-line and providing a backward register output. One of the backward decimation registers (24) which receives data samples in sequence form one of the forward decimation registers can function as both a LIFO and a FIFO register, when a LIFO register, it operates to reverse blocks of data samples wherein the size of each block corresponds to the decimation rate. Each reversed block is then shifted through the backward shifting data section. Each of the other backward decimation registers operates as FIFO register. The decimation circuitry can be used to form a digital filter cascadable into various sizes.</p> |
