| 摘要 |
<p>First, second, third and fourth MOS transistors (Q1-Q4) each have a gate terminal, a first current flowing terminal, and a second current flowing terminal. The first current flowing terminal of the first MOS transistor (Q1) is coupled to the first current flowing terminal of the second MOS transistor (Q2) at a first voltage node (100); the first current flowing terminal of the third MOS transistor (Q3) is coupled to the second current flowing terminal of the first MOS transistor (Q1) at a first output node (139); the first current flowing terminal of the fourth MOS transistor (Q4) is coupled to the second current flowing terminal of the second MOS transistor (Q2) at a second output node (142); and the second current flowing terminal of the fourth MOS transistor (QL) is coupled to the second current flowing terminal of the third MOS transistor (Q3) at a second voltage node (150). A transistor control unit is coupled to the gate terminals of the first, second, third and fourth MOS transistors (Q1-Q4) for biasing the transistors for alternately flowing current through the first and fourth MOS transistors (Q1-Q4) or through the second and third MOS transistors (Q2,Q3). A first transmission line (T1) is coupled to the second output node (14), and a second transmission line (T2) is coupled to the first output node (139). A terminating resistance (RT) is coupled to the first transmission line (T1) and to the second transmission line (T1) for preventing signal reflections on the first transmission line (T1) and the second transmission line (T2). The first transmission line (T1) is coupled to a first input terminal of an ECL circuit element, and the second transmission line (T2) is coupled to a second input terminal of the ECL circuit element. The signals on the first and second transmission lines (T1,T) are used for driving the gates in the ECL circuit element. A source resistance (Rs) is coupled between the first voltage node (100) and a voltage source (VCC). The source resistance (Rs) ensures that the voltage at the first and second output nodes (139,142) do not exceed the saturation values of the driven ECL gates while simultaneously maintaining a strong differential signal across the first and second output nodes (139,142). <IMAGE></p> |
