发明名称 |
Method and apparatus for simultaneous, interleaved access of multiple memories by multiple ports |
摘要 |
A memory system having multiple memories and multiple ports. Multiplexing logic couples each of the ports to each of the memories. A sequencing circuit controls the multiplexers so that each port is sequentially coupled to each of the memories in sequence in a repeating cycle. When coupled to each memory, a block of data is transferred. A second port is coupled to a different memory at each point in time, with the two ports being switched simultaneously to avoid overlap. A port desiring access to the system must wait until it can fit into this switching queue so that it can transfer in lock-step with the other ports to a different memory. Each port has a data I/O bus, an address input bus, an address counter and R/W controls.
|
申请公布号 |
US5202856(A) |
申请公布日期 |
1993.04.13 |
申请号 |
US19900505297 |
申请日期 |
1990.04.05 |
申请人 |
MICRO TECHNOLOGY, INC. |
发明人 |
GLIDER, JOSEPH S.;SHAH, KAUSHIK S.;ASATO, EDWARD E. |
分类号 |
G06F13/16;G11C7/10 |
主分类号 |
G06F13/16 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|