发明名称 Method of controlling a shared memory bus in a multiprocessor system for preventing bus collisions and for ensuring a full bus
摘要 A system and method for controlling a shared memory bus in a computer of a multi-processor system prevents collisions on the shared bus and ensures that the bus is full at system start-up. Steady state operations are maintained without the need for a queuing mechanism in the system's memory controller and in view of the memory modules of the shared memory having different read access times, with the system and method being implemented in a system that includes a central unit and multiple uni-directional buses that are disposed between a shared memory and a plurality of processors, with the central unit controlling access to, and use of, the shared buses of the system.
申请公布号 US5202973(A) 申请公布日期 1993.04.13
申请号 US19900546548 申请日期 1990.06.29
申请人 DIGITAL EQUIPMENT CORPORATION 发明人 RAMANUJAN, RAJ;KELLER, JAMES B.;STICKNEY, JAY;HO, STEVEN;LEMMON, PAUL
分类号 G06F13/16;G06F13/376 主分类号 G06F13/16
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