发明名称 Single-chip-cache-buffer for selectively writing write-back and exclusively writing data-block portions to main-memory based upon indication of bits and bit-strings respectively
摘要 In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.
申请公布号 US5202969(A) 申请公布日期 1993.04.13
申请号 US19920871906 申请日期 1992.04.21
申请人 HITACHI, LTD.;HITACHI VLSI ENGINEERING 发明人 SATO, KATSUYUKI;NISHIMUKAI, TADAHIKO;UCHIYAMA, KUNIO;AOKI, HIROKAZU;HATANO, SUSUMU;OISHI, KANJI;FUKUTA, HIROSHI;KIKUCHI, TAKASHI;SAIGOU, YASUHIKO
分类号 G06F12/08;G11C11/4096 主分类号 G06F12/08
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