| 摘要 |
A variable frequency synthesizer including a modulo N counter having a count limit N that is a product of prime numbers and responsive to a digital control word for providing a digital ramp signal representative of the phase of a sinewave, an inversion circuit responsive to the digital ramp signal for producing a digital triangular signal having a frequency determined by the control word, and conversion means for converting the digital triangular signal to an analog triangular signal. Selecting the count limit N as a product of prime numbers substantially reduces spurious distortion due to time step quantization of the digital ramp signal.
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