| 摘要 |
PURPOSE:To reduce the transmission delay of a signal due to a wire length. CONSTITUTION:Voltage divider resistors Ra, Rb, Rc and Rd are provided on the way of a wire 1 and the other terminal of them is connected to the wire 1 through PMOS 3, NMOS 4, PMOS 5, NMOS 6. The PMOS 3 and the NMOS 4 are turned on for a prescribed time before a VCLOCK comes when a voltage Vx at an input terminal of a latch circuit 2 is logical H and the PMOS 5 and the NMOS 6 are turned on for a prescribed time before the VCLOCK comes when the voltage Vx at the input terminal of the latch circuit 2 is logical L. Since a potential on the way of the wire 1 is changed to a level in the vicinity of a threshold level of the latch circuit 2 before an inverted output of a VIN is sent to the wire 1, the transmission delay in the signal is reduced. |
