发明名称 PLL SYSTEM FREQUENCY SYNTHESIZER CIRCUIT
摘要 PURPOSE:To make immediately a frequency of a frequency synthesizer selected at a high speed stable by connecting plural loop filters whose pass band differs switchingly to a common phase locked loop circuit. CONSTITUTION:The circuit is provided with two loop filters 3-1, 3-2 and ON/ OFF switches 7a-1, 7b-1 (7a-2, 7b-2) are connected respectively to a pre-stage and a post-stage of the filter 3-1 (3-2), the ON/OFF state is controlled by a control circuit 6 to connect the loop filters 3-1, 3-2 into a phase locked loop (PLL) alternately. Thus, the 1st and 2nd steady-states are once attained respectively by the 1st and 2nd loop filters 3-1, 3-2 and the stable operating state is switched almost immediately between 1st and 2nd frequencies f1, f2 by selecting a frequency division ratio of a frequency divider 5 corresponding to 1st or 2nd frequency data and also selecting the switches 7a-1, 7b-1 and 7a-2, 7b-2 thereby implementing high speed frequency hopping.
申请公布号 JPH0590993(A) 申请公布日期 1993.04.09
申请号 JP19910234856 申请日期 1991.09.13
申请人 UNIDEN CORP 发明人 MAEDA KAZUO
分类号 H03L7/107;H03L7/18;H04B1/40 主分类号 H03L7/107
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